منابع مشابه
Parallel VLSI architecture for MAP turbo decoder
Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires many iterations and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. Late...
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2016
ISSN: 2169-3536
DOI: 10.1109/access.2016.2581978